In a semiconductor memory, the threshold voltage of a memory cell can be changed by changing the amount of electric charge stored in a storage layer of the memory cell. Therefore, by storing a different amount of electric charge, the memory cell can store different data. For example, for a single-bit memory cell, the state without electric charge in the storage layer represents a logic 0 or 1 while the state with electric charge in the storage layer represents a logic 1 or 0. As another example, in a multi-bit memory cell, such as a two-bit memory cell, different states represent logics 00, 01, 10, and 11, respectively, by storing different amounts of charge. The memory cell in different states has different threshold voltages corresponding to the different states. Therefore, to determine the data stored in the memory cell, a read voltage higher than the threshold voltage of the memory cell in a lower-threshold state and lower than that in a higher-threshold state is applied to the memory cell to determine whether the memory cell has been programmed to the higher-threshold state.
The process for storing date into memory cells of a semiconductor memory is also referred to as “programming.” During a programming process of a semiconductor memory, a programming voltage is applied to certain memory cells to inject electric charge into the storage layer of each of these memory cells, to program these memory cells to a higher-threshold state. However, since memory cells in a semiconductor memory are arranged closely to each other, programming one memory cell may influence a neighboring memory cell, thus accidentally changing the threshold voltage of the neighboring memory cell. This phenomenon is also referred to as “program disturbance.”
For example, in a semiconductor memory including single-bit memory cells, the memory cells are programmed page by page, where each page includes memory cells coupled to the same word line. In the present disclosure, the term “word line” also refers to the collection of memory cells coupled to that word line. Thus, a memory cell coupled to a word line is also referred to as a memory cell of or belonging to that word line. The memory cells in a page fall into two groups after being programmed, one having lower threshold voltages and the other one having higher threshold voltages. In practice, the memory cells in the same group may not have exactly the same threshold voltage, but have threshold voltages within a certain range. For example, the memory cells in the low-threshold state may have threshold voltages within the range of VL1 to VL1, while the memory cells in the high-threshold state may have threshold voltages within the range of VH1 to VH2. Whether a memory cell is in the low-threshold state or in the high-threshold state (and thus whether the memory cell stores a logic 0 or a logic 1) can be determined by applying a read voltage VR that is higher than VL2 but lower than VH1 and determining whether the memory cell is on or off.
However, due to program disturbance, when one page is programmed, a neighboring page may be affected. Thus, in the neighboring page, the threshold voltage range of the memory cells in the low-threshold state may shift to the range of VL1′-VL2′ and the threshold voltage range of the memory cells in the high-threshold state may shift to the range of VH1′-VH2′. If the previously chosen read voltage VR is smaller than VL2′, then some of the memory cells that are actually in the low-threshold state will be incorrectly determined to be in the high-threshold state. Thus, in this case, to more accurately determine the state of the memory cells, a different read voltage VR′ that is higher than VL2′ but lower than VH1′ should be used.
Table 1 and FIGS. 1A-1E schematically illustrate another example involving a semiconductor memory including two-bit memory cells. Table 1 shows an exemplary programming scheme in the semiconductor memory including two-bit memory cells. In this example, one block of the semiconductor memory is illustrated. The memory cells in this block are separated into 128 groups, each of which belongs to one word line (WL), numbered as 0, 1, . . . 127, as shown in Table 1. Each of the memory cells can store a least significant bit (LSB) and a most significant bit (MSB). The LSBs or the MSBs of the same word line form a page and thus the semiconductor memory includes a total of 256 pages. During the programming process, the semiconductor memory is programmed page by page and, as shown in Table 1, the pages are numbered as 0, 1, . . . 255, according to the order of programming. For example, page 0 includes the LSBs of WL 0 and is first programmed, page 1 includes the LSBs of WL 1 and is then programmed, and page 255 includes the MSBs of WL 127, and is last programmed.
TABLE 1Page Program OrderWLLSBMSB00211423635847   252126251254127253255
FIGS. 1A-1E schematically show, as an example, the distribution of memory cells of WL 2 after pages 3, 4, 5, 6, and 8 are programmed, respectively. In the present disclosure, the distribution of memory cells of a word line refers to a plot of the number of memory cells as a function of threshold voltage. For example, in FIGS. 1A-1E, the horizontal axis represents the threshold voltage and the vertical axis represents the number of memory cells having a certain threshold voltage. Referring again to Table 1, pages 3 and 6 belong to WL 2, while pages 4, 5, and 8 belong to one of the neighboring word lines (WL 1 and WL 3) of WL 2, and are programmed after one or two pages in WL 2 are programmed.
As shown in FIG. 1A, after page 3 (LSBs on WL 2) is programmed, the memory cells on WL 2 are separated into two groups. At this time, the ideal read voltage for determining the state of a memory cell in WL 2 is VR3. As shown in FIG. 1B, after page 4 is programmed, the distribution of WL 2 memory cells is shifted by a disturbance Δ4 due to the influence of the programming of page 4 on the WL 2 memory cells. Such a disturbance is also referred to as a “program disturbance.” Due to this shift, if VR3 is still used as the read voltage after page 4 is programmed, some of the WL 2 memory cells that are actually in the low-threshold state will be incorrectly determined as being in the high-threshold state. Therefore, to reduce error, a different ideal read voltage VR4 should be used at this time for determining the state of the memory cells on WL 2. Similarly, as shown in FIG. 1C, programming page 5 introduces a disturbance Δ5 into the distribution of the WL 2 memory cells and the ideal read voltage at this time becomes VR5.
Further, as shown in FIG. 1D, after page 6 (MSBs on WL 2) is programmed, the memory cells on WL 2 are further separated into four groups, representing logic 00, 01, 10, and 11, respectively. At this time, the ideal read voltages for determining the state of a memory cell on WL 2 are VR6L, VR6M1, and VR6M2, respectively, where VR6L is used to determine the least significant bit stored in the memory cell and VR6M1 and VR6M2 are used to determine the most significant bit stored in the memory cell. After page 8 is programmed, as shown in FIG. 1E, the distribution of WL 2 memory cells are further shifted by a disturbance Δ8 due to the influence of the programming of page 8 on the WL 2 memory cells. As a consequence, the ideal read voltages become VR8L, VR8M1, and VR8M2, respectively.
As can be seen from the above-described examples, if the same read voltage(s) are used at different stages of programming a semiconductor memory, some memory cells may be “mis-read,” and thus the bit-error rate may be high.